1. Technical Field
The present invention relates to a method and system for data processing in general and, in particular, to a method and system for handling
Peripheral Component Interconnect (PCI) peer-to-peer accesses within a computer system. Still more particularly, the present invention relates to a method and system for translating PCI peer-to-peer access across multiple PCI host bridges within a computer system.
2. Description of the Prior Art
A computer system typically includes several types of buses, such as system bus, local buses, and peripheral buses. Various electronic circuit devices and components are connected with each other via these buses such that intercommunication may be possible among all of these devices and components.
In general, a central processing unit (CPU) is attached to a system bus, over which the CPU communicates directly with a system memory that is also attached to the system bus. A local bus is intended for connecting certain highly integrated peripheral components on the same bus as the CPU. One such local bus is known as the Peripheral Component Interconnect (PCI) bus. Under the PCI local bus standard, peripheral components can directly connect to a PCI local bus without the need for glue logic. Thus, PCI provides a bus standard on which high-performance peripheral devices, such as graphics devices and hard disk drives, can be coupled to the CPU, thereby permitting these high-performance peripheral devices to avoid the general access latency and the bandwidth constraints that are associated with a peripheral bus. A peripheral bus such as an Industry Standard Architecture (ISA) bus, is for connecting various peripheral devices to the computer system. These peripheral devices typically include input/output (I/O) devices such as a keyboard, floppy drives, and printers.
Generally, each system bus, local bus, and peripheral bus utilizes an independent set of protocols (or rules) to conduct data transfers between various devices attached to it. Each of these protocols is designed into a bus directly and is commonly referred to as the "architecture" of the bus. In a data transfer between different bus architectures, data being transferred from the first bus architecture may not be in a form that is usable or intelligible by the receiving second bus architecture. Accordingly, a mechanism is developed for "translating" data that are required to be transferred from one bus architecture to another. This translation mechanism is normally contained in a hardware device in the form of a bus-to-bus bridge (or interface) through which the two different types of buses are connected.
Incidentally, various bus-to-bus bridges have been designed to match the communication protocol of one bus with that of another in order to permit system-wide communications between devices on different buses. For example, a bus-to-bus bridge connecting between a system bus and a PCI local bus is called a PCI host bridge. The PCI host bridge contains all the logic and hardware for translating data communications between the system bus and the PCI local bus, and ensures that data is transferred between these two buses intelligibly.
In a PCI-based system where there are multiple PCI host bridges, there needs to be a way, however, for a PCI host bridge to differentiate as to whether a PCI device, during a direct memory access (DMA) request, is trying to access the system memory or another PCI device. Further, if the requesting PCI device is trying to access another PCI device, i.e., a peer-to-peer access, the PCI host bridge also needs to determine whether the other PCI device is under the same PCI host bridge as the requesting PCI device or under a different PCI host bridge.
A peer-to-peer access typically has some different characteristics than a DMA access to the system memory. Some of these differences can be attributed to the fact that an access to a PCI memory may have side effects depending on how the access is performed, such as the order of the access, the width of the access, etc. For example, prefetching more data on a read operation than what a requesting PCI device is requesting can cause a problem. This is because a read access to addresses on a PCI device may cause side effects, and accessing data outside of what is requested may also have undesirable side effects. In addition, a PCI local bus may allow some unusual operations that are typically not supported by the system interconnect to which the PCI host bridge is attached. As an example, the PCI local bus allows discontiguous bytes to be accessed within a single 4-byte or 8-byte access. If this discontiguous access were to be allowed for peer-to-peer transactions, and if the system interconnect does not support such discontiguous transaction without breaking up the transaction (which is a high probability), and if this discontiguous transaction causes different side effects to the transaction when broken up, then the peer to-peer transaction would probably not function properly when such is attempted to perform across multiple PCI host bridges. Thus, in order to support peer-to-peer transactions across multiple PCI host bridges, additional requirements are necessary. Some of these requirements affect the way a PCI host bridge operates, and some put certain restrictions on the transactions that are allowed by a peer-to-peer access. The additional rules and requirements for supporting PCI peer-to-peer access across multiple PCI host bridges are the subject matter of the present disclosure.